1. Field of the Invention
The present invention relates to bus arbitration. In one example, the present invention relates to methods and apparatus for implementing a bus arbitration priority encoding scheme with fairness.
2. Description of Related Art
A system implemented programmable chip typically includes multiple primary components such as processors and multiple secondary components such as timers and memory interconnected using one or more buses. A system implemented on a programmable chip provides a number of benefits as well as drawbacks. One drawback is that programmable chip buses are typically slower than comparable buses on specialized devices such as Application Specific Integrated Circuits (ASICs). Buses use arbitration logic to handle requests from the primary components for bus access to communicate with secondary components. Arbitration logic selects a bus master at any given time. Bus arbitration logic efficiency can significantly impact system performance.
It is typically beneficial to implement bus arbitration schemes that provide priority and fairness considerations. For example, there may be some higher priority components that deserve at greater share or bus access time. However, no primary component should be entirely locked out of bus access. Providing both priority and fairness considerations, however, can lead to inefficient and complicated arbitration logic chains on programmable chips. Consequently, many programmable chip bus arbiters are kept relatively simple. In many instances, programmable chip bus arbiters consider priority only and do not consider fairness. Consequently, some components may be provided with an undesirably disproportionate share of total bus access.
It is therefore desirable to provide improved methods and apparatus for implementing efficient bus arbitration schemes that provide fairness and/or priority considerations when selecting primary components for access to a programmable chip bus.